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A 10-bit, 1.8-GS/s Time-Interleaved Pipeline ADC.
Väinö Hakkarainen
Arto Rantala
Mikko Aho
Jaana Riikonen
David Gomes-Martin
Markku Åberg
Kari Halonen
Published in:
ICECS (2007)
Keyphrases
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analog to digital converter
pipeline architecture
video sequences
random access memory
bit vectors
database
data sets
artificial intelligence
data structure
error correction
processing pipeline
bit vector
magnetic tape