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Technology optimised fixed-point bit-parallel multiplier for LUT-based FPGAs.
Burhan Khurshid
Roohie Naaz Mir
Published in:
Int. J. High Perform. Syst. Archit. (2016)
Keyphrases
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fixed point
floating point
lookup table
bit parallel
pattern matching
sufficient conditions
dynamical systems
belief propagation
hardware implementation
fixed point theorem
variational inequalities
higher order
constraint databases
pairwise