VLSI architecture for 4×4 16-QAM V-BLAST decoder.
Fariborz SobhanmaneshSaeid NooshabadiPublished in: ISCAS (2006)
Keyphrases
- vlsi architecture
- low complexity
- distributed video coding
- vlsi implementation
- low density parity check
- low power
- motion estimation
- real time
- bit error rate
- channel coding
- computational complexity
- physical layer
- bit plane
- fading channels
- unequal error protection
- error concealment
- ldpc codes
- error resilient
- mode decision
- computer vision
- video streaming
- turbo codes
- power consumption
- coding scheme
- multipath
- source coding
- multiscale
- video codec