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24.3 A 3nm Gate-All-Around SRAM Featuring an Adaptive Dual-BL and an Adaptive Cell-Power Assist Circuit.

Taejoong SongWoojin RimHoonki KimKeun Hwi ChoTaeyeong KimTaejung LeeGeumjong BaeDong-Won KimS. D. KwonSanghoon BaekJonghoon JungJongwook KyeHakchul JungHyungtae KimSoon-Moon JungJaehong Park
Published in: ISSCC (2021)
Keyphrases
  • cmos technology
  • power consumption
  • power reduction
  • power dissipation
  • low power
  • real time
  • nm technology
  • data sets
  • online learning
  • low voltage
  • silicon on insulator