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A Systematic Design of Tamper-Resistant Galois-Field Arithmetic Circuits Based on Threshold Implementation with (d + 1) Input Shares.
Rei Ueno
Naofumi Homma
Takafumi Aoki
Published in:
ISMVL (2017)
Keyphrases
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high level synthesis
circuit design
efficient implementation
implementation issues
galois field
logic synthesis
design process
design methodology
design considerations
user interface
data integration
fixed point
cmos technology
electronic circuits
parallel distributed