Underapproximation for model-checking based on universal circuits.
Arie MatsliahOfer StrichmanPublished in: Inf. Comput. (2010)
Keyphrases
- ordered binary decision diagrams
- model checking
- deterministic finite automaton
- asynchronous circuits
- temporal logic
- symbolic model checking
- formal verification
- automated verification
- temporal properties
- formal specification
- finite state machines
- model checker
- process algebra
- partial order reduction
- reachability analysis
- computation tree logic
- pspace complete
- concurrent systems
- formal methods
- finite state
- epistemic logic
- transition systems
- artifact centric
- verification method
- bounded model checking
- timed automata
- linear temporal logic
- reactive systems
- domain independent