Design of a low power GPS receiver in 0.18 µm CMOS technology with a SigmaDeltafractional-N synthesizer.
Di LiYintang YangJiang-an WangBing LiQiang LongJary WeiNai-di WangLei WangQiankun LiuDa-long ZhangPublished in: J. Zhejiang Univ. Sci. C (2010)
Keyphrases
- low power
- cmos technology
- power consumption
- single chip
- low cost
- high speed
- power dissipation
- low power consumption
- mixed signal
- vlsi architecture
- logic circuits
- digital signal processing
- low voltage
- gate array
- parallel processing
- design process
- power reduction
- computer vision
- circuit design
- embedded systems
- ultra low power