On the way to the 2.5 Gbits/s ATM network ATM multiplexer demultiplexer ASIC.
Jacobo RiescoJuan C. DíazLuis A. MerayoJosé Luis ConesaCarlos SantosEduardo Juárez MartínezPublished in: ED&TC (1997)
Keyphrases
- atm networks
- integrated circuit
- admission control
- asynchronous transfer mode
- hardware implementation
- application specific
- design methodology
- real time traffic
- hardware architecture
- allocation scheme
- end to end
- scheduling problem
- multiresolution
- resource consumption
- reinforcement learning
- genetic algorithm
- real time