System architecture of an adaptive reconfigurable DSP computing engine.
An-Yeu WuK. J. Ray LiuArun RaghupathyPublished in: IEEE Trans. Circuits Syst. Video Technol. (1998)
Keyphrases
- systolic array
- hardware implementation
- reconfigurable architecture
- signal processing
- real time
- heterogeneous computing
- digital signal
- digital signal processor
- data flow
- layered architecture
- digital signal processing
- learning algorithm
- texas instruments
- inference engine
- fine grain
- parallel architecture
- design considerations
- associative memory
- software architecture
- high speed
- general purpose