Leveraging Hardware QoS to Control Contention in the Xilinx Zynq UltraScale+ MPSoC.
Alejandro Serrano-CasesJuan M. ReinaJaume AbellaEnrico MezzettiFrancisco J. CazorlaPublished in: ECRTS (2021)
Keyphrases
- hardware implementation
- quality of service
- control program
- hardware architecture
- real time
- data acquisition
- field programmable gate array
- low cost
- control system
- high speed
- hardware and software
- fpga implementation
- web services
- hardware description language
- computing systems
- response time
- real time embedded
- control strategy
- mobile robot