A High Speed, Low Memory FPGA Based LDPC Decoder Architecture for Quasi-Cyclic LDPC Codes.

Paul Saunders Anthony D. Fagan

Published in: FPL (2006)

Keyphrases

ldpc codes
low memory
high speed
low density parity check
decoding algorithm
error correction
message passing
image transmission
rate allocation
channel coding
source coding
vlsi architecture
forward error correction
transform coding
non binary
image coding
video coding