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A Time-Domain Wavefront Computing Accelerator With a 32 × 32 Reconfigurable PE Array.
Chengshuo Yu
Junjie Mu
Yuqi Su
Kevin Tshun Chuan Chai
Tony Tae-Hyoung Kim
Bongjin Kim
Published in:
IEEE J. Solid State Circuits (2023)
Keyphrases
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field programmable gate array
low cost
frequency domain
programmable logic
general purpose
reconfigurable architecture
genetic algorithm
systolic array
parallel implementation
real time
machine learning
feature selection
artificial neural networks
hardware implementation