Optimised fault tolerant core-based ASIC design for SRAM.

T. Suresh Z. Brijet

Published in: Int. J. Manuf. Technol. Manag. (2021)

Keyphrases

fault tolerant
fault tolerance
distributed systems
load balancing
design methodology
design process
high availability
safety critical
response time
embedded systems
circuit design
state machine
hardware implementation
computer architecture