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Bounding Memory Access Times in Multi-Accelerator Architectures on FPGA SoCs.
Francesco Restuccia
Marco Pagani
Alessandro Biondi
Mauro Marinoni
Giorgio C. Buttazzo
Published in:
IEEE Trans. Computers (2023)
Keyphrases
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memory access
field programmable gate array
memory hierarchy
memory management
hardware implementation
data access
main memory
shared memory
external memory
low cost
signal processing
data mining
operating system
real time
processing units
data management
data structure