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A 6.16Gb/s 4.7pJ/bit/iteration LDPC decoder for IEEE 802.11ad standard in 40nm LP-CMOS.
Hiroyuki Motozuka
Naoya Yosoku
Takenori Sakamoto
Takayuki Tsukizawa
Naganori Shirakata
Koji Takinami
Published in:
GlobalSIP (2015)
Keyphrases
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high speed
low density parity check
objective function
linear programming
power consumption
distributed video coding
ldpc codes
nm technology
low cost
random access memory
low power
turbo codes
cmos technology
successive approximation
linear program