A Fully Parallel, High-Speed BPC Hardware Architecture for the EBCOT in JPEG 2000.
Dong-Hwi WooKyeong-Ryeol BaeHyeon-Sik SonSeung-Ho OkYong-Hwan LeeByungin MoonPublished in: FGIT-FGCN (2) (2010)
Keyphrases
- hardware architecture
- high speed
- processing elements
- compression ratio
- hardware implementation
- bit plane
- hardware architectures
- image compression
- associative memory
- low power
- parallel implementation
- image coding
- field programmable gate array
- compression algorithm
- general purpose
- pattern recognition
- frame rate
- parallel computing
- parallel processing
- data processing
- distributed memory
- parallel processors
- image quality
- signal processing
- xilinx virtex