The FFT butterfly operation in 4 processor cycles on a 24 bit fixed-point DSP with a pipelined multiplier.
Martin GrajcarBernhard SickPublished in: ICASSP (1997)
Keyphrases
- fixed point
- floating point
- instruction set
- instruction set architecture
- signal processing
- sufficient conditions
- dynamical systems
- floating point unit
- high speed
- lookup table
- belief propagation
- data flow
- systolic array
- parallel architecture
- variational inequalities
- fixed point theorem
- constraint databases
- free energy
- level set
- graphical models