An Efficient Hardware Architecture for Packet Re-sequencing in Network Processors MPSoCs.
Shadi TraboulsiMichael MeitingerRainer OhlendorfAndreas HerkersdorfPublished in: DSD (2009)
Keyphrases
- hardware architecture
- packet switching
- network structure
- internet traffic
- network devices
- peer to peer
- hardware implementation
- processing elements
- packet size
- parallel algorithm
- network traffic
- real time
- parallel processing
- packet filtering
- hardware architectures
- distributed systems
- wireless sensor networks
- feature extraction
- machine learning
- neural network