Modeling and optimization of low power resonant clock mesh.

Wulong Liu Guoqing Chen Yu Wang Huazhong Yang

Published in: ASP-DAC (2015)

Keyphrases

low power
power consumption
high speed
low cost
wireless transmission
high power
gate array
logic circuits
vlsi architecture
single chip
digital signal processing
vlsi circuits
power saving
power reduction
mixed signal
delay insensitive
nm technology