Prefetching across a shared memory tree within a Network-on-Chip architecture.
Jamie GarsideNeil C. AudsleyPublished in: ISSoC (2013)
Keyphrases
- multi processor
- shared memory
- network on chip
- prefetching
- response time
- message passing
- parallel algorithm
- distributed memory
- parallel architecture
- parallel computing
- program execution
- parallel programming
- single processor
- parallel computers
- parallel computation
- web documents
- parallel machines
- parallel architectures
- memory access
- multi core processors