A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency in 40-nm CMOS.
Zhao ZhangZhaoyu ZhangYong ChenNan QiJian LiuNanjian WuLiyuan LiuPublished in: VLSI Technology and Circuits (2023)
Keyphrases
- power consumption
- energy efficiency
- nm technology
- low power
- cmos technology
- power management
- power saving
- high speed
- energy efficient
- battery powered
- data center
- energy saving
- energy management
- high performance computing
- energy consumption
- traffic load
- energy conservation
- energy aware
- network lifetime
- wireless sensor
- wireless sensor networks
- computer vision
- power dissipation
- packet loss
- reduce the energy consumption
- database systems
- low cost
- sensor networks