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A Robust High Speed Serial PHY Architecture With Feed-Forward Correction Clock and Data Recovery.

William Redman-WhiteMartin BugbeeSteve DobbsXinyan WuRichard A. H. BalmfordJonah NuttgensUmer Salim KianiRichard CleggGerrit W. den Besten
Published in: IEEE J. Solid State Circuits (2009)
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