Video DSP architecture for MPEG2 codec.
Toshiyuki ArakiMasaki ToyokuraToshihide AkiyamaHiroshi TakenoBrent WilsonKunitoshi AonoPublished in: ICASSP (2) (1994)
Keyphrases
- video decoder
- video codec
- bitstream
- video coding
- low power consumption
- motion jpeg
- compressed video
- compression standards
- multimedia
- video sequences
- coding scheme
- digital video
- real time
- bit rate
- mpeg standard
- platform independent
- signal processing
- video frames
- inter frame
- video content
- mpeg video
- video compression
- transform domain
- video quality
- texas instruments
- motion compensation
- video data
- video transcoding
- high speed
- systolic array
- variable bit rate
- digital television
- scalable video codec
- intra frame
- digital signal processing
- scalable video
- video signals
- scalable video coding
- rate distortion
- compressed domain
- data flow
- motion compensated
- video surveillance
- video streams