A Highly Parallel Architecture for Deblocking Filter in H.264/AVC.
Lingfeng LiSatoshi GotoTakeshi IkenagaPublished in: IEICE Trans. Inf. Syst. (2005)
Keyphrases
- deblocking filter
- highly parallel
- low power
- single chip
- low bit rate
- blocking artifacts
- video communication
- efficient implementation
- spatial domain
- motion compensation
- computing systems
- parallel architectures
- post processing
- image quality
- variable block size
- real time
- single pass
- low cost
- video streaming
- high definition
- high speed
- power consumption
- transform domain
- visual quality
- video coding