A Low-Power and Highly Linear 14-bit Parallel Sampling TDC With Power Gating and DEM in 65-nm CMOS.
Supeng LiuYuanjin ZhengPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2016)
Keyphrases
- low power
- power consumption
- cmos technology
- nm technology
- high power
- bit parallel
- power reduction
- low cost
- power management
- high speed
- silicon on insulator
- power dissipation
- single chip
- power saving
- ultra low power
- pattern matching
- vlsi architecture
- vlsi circuits
- logic circuits
- low voltage
- mixed signal
- image sensor
- low power consumption
- delay insensitive
- energy dissipation
- cmos image sensor
- digital signal processing
- regular expressions
- parallel processing