Operation chaining asynchronous pipelined circuits.

Girish Venkataramani Seth Copen Goldstein

Published in: ICCAD (2007)

Keyphrases

delay insensitive
shift register
asynchronous circuits
high level synthesis
high speed
real time
machine learning
analog vlsi
information systems
data flow
parallel architecture
logic circuits
linear array
real world
logic synthesis
neural network
database