32 Bit re-configurable RISC processor design and implementation for BETA ISA with inbuilt matrix multiplier.
Raj Prakash SinghAnkit K. VashishthaR. KrishnaPublished in: ISED (2016)
Keyphrases
- instruction set
- instruction set architecture
- floating point
- hardware architecture
- xilinx virtex
- computer architecture
- hardware implementation
- design process
- single chip
- implementation issues
- case study
- computation intensive
- high speed
- application specific
- memory management
- embedded systems
- design considerations
- rapid prototyping
- circuit design
- parallel implementation
- efficient implementation