Combining supervisor synthesis and model checking.
Roberto ZillerKlaus SchneiderPublished in: ACM Trans. Embed. Comput. Syst. (2005)
Keyphrases
- model checking
- temporal logic
- formal verification
- model checker
- finite state
- automated verification
- temporal properties
- symbolic model checking
- formal specification
- bounded model checking
- timed automata
- computation tree logic
- partial order reduction
- reachability analysis
- transition systems
- epistemic logic
- verification method
- process algebra
- artificial intelligence
- pspace complete
- finite state machines
- asynchronous circuits
- linear temporal logic
- formal methods
- binary decision diagrams