A Low Power 50MHz FFT Processor with Cyclic Extension and Shaping Filter.
Mark A. BickerstaffT. ArivoliPhilip J. RyanNeil WesteDavid J. SkellernPublished in: ASP-DAC (1998)
Keyphrases
- low power
- high speed
- single chip
- gate array
- cmos technology
- power consumption
- deblocking filter
- low cost
- nm technology
- fast fourier transform
- wireless transmission
- vlsi architecture
- real time
- high power
- logic circuits
- frequency domain
- low power consumption
- vlsi circuits
- digital signal processing
- power reduction
- mixed signal
- general purpose
- subband
- efficient implementation