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A ΔΣ DPLL with 1b TDC, 4b DTC and 8-tap FIR filter for low-voltage clock generation/modulation systems.
Xiaohua Huang
Han Liu
Woogeun Rhee
Zhihua Wang
Published in:
VLSI-DAT (2018)
Keyphrases
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low voltage
high speed
computer systems
fir filters
computer vision
digital images
computing systems