A 2.1 M Pixels, 120 Frame/s CMOS Image Sensor With Column-Parallel Delta Sigma ADC Architecture.
Youngcheol ChaeJimin CheonSeunghyun LimMinho KwonKwisung YooWunki JungDong-Hun LeeSeogheon HamGunhee HanPublished in: IEEE J. Solid State Circuits (2011)
Keyphrases
- analog to digital converter
- cmos image sensor
- delta sigma
- parallel processing
- dynamic range
- single chip
- solid state
- processing capabilities
- low power
- image sensor
- image enhancement
- low power consumption
- sensor technology
- low cost
- input image
- image compression
- vision system
- data storage
- motion estimation
- spatial correlation
- signal processing