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Post Optimization of a Clock Tree for Dynamic Clock Tree Power Reduction in 45 nm and Below Technology Nodes.

Biswajit PatraAmlan ChakrabartiSanatan Chattopadhyay
Published in: J. Low Power Electron. (2014)
Keyphrases
  • power consumption
  • power reduction
  • tree nodes
  • leaf nodes
  • high speed
  • low power
  • computer systems
  • real time
  • index structure
  • fine grained
  • cost effective
  • data center
  • b tree
  • clock gating