Model Checking of Embedded Assembly Program Based on Simulation.
Satoshi YamaneRyosuke KonoshitaTomonori KatoPublished in: IEICE Trans. Inf. Syst. (2017)
Keyphrases
- model checking
- temporal logic
- formal verification
- symbolic model checking
- temporal properties
- model checker
- dynamic analysis
- partial order reduction
- automated verification
- formal specification
- verification method
- bounded model checking
- reachability analysis
- finite state machines
- finite state
- computation tree logic
- timed automata
- process algebra
- formal methods
- transition systems
- concurrent systems
- embedded systems
- pspace complete
- epistemic logic
- reactive systems
- control flow
- petri net
- modal logic