Login / Signup
A low power and jitter delay cell with pulse width modulation for wide range delay lock loops.
Shahram Modanlou
Gholamreza Ardeshir
Mohammad Gholami
Published in:
Microelectron. J. (2021)
Keyphrases
</>
low power
power dissipation
power consumption
high speed
low cost
vlsi architecture
digital signal processing
neural network
logic circuits
low power consumption
fuzzy logic
numerical simulations
cmos technology
pulse width modulation
gate array
ultra low power