Minimal Path Delay Leading Zero Counters on Xilinx FPGAs.

Gregory Morse Tamás Kozsik Peter Rakyta

Published in: ICCS (3) (2023)

Keyphrases

minimal path
field programmable gate array
endpoints
hardware implementation
tubular structures
fpga implementation
active contour model
embedded systems
minimal paths
high speed
parallel computing
hardware architecture
minimal surface
image processing algorithms
line segments
efficient implementation