High-Performance Pipelined Architecture for Tree-Based IP Lookup Engine on FPGA.

Yun Qu Viktor K. Prasanna

Published in: IPDPS Workshops (2013)

Keyphrases

pipelined architecture
ip address
field programmable gate array
hardware implementation
low power consumption
parallel computing
neural network
ip networks
internet protocol
fpga implementation
computer vision
feature extraction
multi agent systems
high speed
fine grained
ddos attacks