A scaleable instruction buffer for a configurable DSP core.

Christian Panis Michael Bramberger Herbert Grünbacher Jari Nurmi

Published in: ESSCIRC (2003)

Keyphrases

signal processing
digital signal processor
multimedia
digital signal processing
computer technology
computer software
database
real time
data sets
high speed
learning styles
instructional design
instruction set
systolic array
learning disabled students