A systematic approach to transforming system requirements into model checking specifications.
Daniel AceitunaHyunsook DoSudarshan SrinivasanPublished in: ICSE Companion (2014)
Keyphrases
- model checking
- automated verification
- model checker
- formal specification
- transition systems
- bounded model checking
- formal verification
- temporal logic
- reactive systems
- concurrent systems
- finite state machines
- temporal properties
- finite state
- reachability analysis
- formal methods
- partial order reduction
- computation tree logic
- asynchronous circuits
- verification method
- symbolic model checking
- process algebra
- timed automata
- specification language
- automated reasoning
- pspace complete
- epistemic logic
- control flow
- alternating time temporal logic
- abstract interpretation
- deterministic finite automaton
- real time systems