A 10-bit 300MSample/s pipelined ADC using time-interleaved SAR ADC for front-end stages.

Young-Hwa Kim Jaewon Lee SeongHwan Cho

Published in: ISCAS (2010)

Keyphrases

analog to digital converter
sar images
back end
multistage
synthetic aperture radar
data structure
data flow
gray level
image reconstruction
sigma delta