Architectural timing verification of CMOS RISC processors.
Pradip BoseS. SuryaPublished in: IBM J. Res. Dev. (1995)
Keyphrases
- instruction set
- asynchronous circuits
- delay insensitive
- parallel processing
- low cost
- model checking
- parallel algorithm
- high speed
- power consumption
- application specific
- multiprocessor systems
- power supply
- vlsi circuits
- cmos technology
- formal verification
- signature verification
- parallel computing
- circuit design
- high end
- floating point
- embedded systems
- low power consumption
- software architecture
- computer architecture
- face verification
- parallel processors
- low power
- verification method
- high level