A low power TDC with 0.5ps resolution for ADPLL in 40nm CMOS.
Xusong LiuLei MaJunhui XiangNa YanHaolv XieXiaowei CaiPublished in: ASICON (2015)
Keyphrases
- low power
- cmos technology
- nm technology
- power consumption
- high speed
- low cost
- user friendly
- single chip
- low voltage
- vlsi circuits
- high power
- digital signal processing
- image sensor
- power reduction
- silicon on insulator
- phase locked loop
- logic circuits
- mixed signal
- wireless transmission
- low power consumption
- power management
- vlsi architecture
- power dissipation
- high resolution
- real time
- ultra low power