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Quantum-dot cellular automata based reversible low power parity generator and parity checker design for nanocommunication.
Jadav Chandra Das
Debashis De
Published in:
Frontiers Inf. Technol. Electron. Eng. (2016)
Keyphrases
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low power
logic circuits
single chip
low cost
power consumption
high speed
low power consumption
vlsi architecture
digital signal processing
cellular automata
gate array
cmos technology
error correction
high power
mixed signal
cmos image sensor
embedded systems
parallel processing
design process
ultra low power