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A 2.8-3.2-GHz Fractional- N Digital PLL With ADC-Assisted TDC and Inductively Coupled Fine-Tuning DCO.
Chih-Wei Yao
Alan N. Willson Jr.
Published in:
IEEE J. Solid State Circuits (2013)
Keyphrases
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fine tuning
viable alternative
fine tune
high speed
sigma delta
fine tuned
neural network
frequency band
circuit design
data sets
image processing
general purpose
digital topology
hurst exponent