Stateless Model Checking under a Reads-Value-From Equivalence.
Pratyush AgarwalKrishnendu ChatterjeeShreya PathakAndreas PavlogiannisViktor TomanPublished in: CoRR (2021)
Keyphrases
- model checking
- temporal logic
- temporal properties
- formal verification
- formal specification
- automated verification
- model checker
- symbolic model checking
- finite state
- partial order reduction
- finite state machines
- timed automata
- reachability analysis
- transition systems
- computation tree logic
- bounded model checking
- verification method
- concurrent systems
- epistemic logic
- pspace complete
- formal methods
- process algebra
- linear temporal logic
- reactive systems
- asynchronous circuits
- artificial intelligence
- deterministic finite automaton