A 55fJ/conv-step hybrid SAR-VCO ΔΣ capacitance-to-digital converter in 40nm CMOS.
Arindam SanyalNan SunPublished in: ESSCIRC (2016)
Keyphrases
- high speed
- low power
- analog to digital converter
- metal oxide semiconductor
- cmos technology
- low voltage
- circuit design
- data conversion
- mixed signal
- power consumption
- real time
- low cost
- nm technology
- control method
- cmos image sensor
- silicon on insulator
- input output
- image processing
- power dissipation
- integrated circuit
- image reconstruction
- post processing