Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning.
Grace Li ZhangBing LiJinglan LiuYiyu ShiUlf SchlichtmannPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2018)
Keyphrases
- iterative learning
- buffer allocation
- high speed
- buffer management
- queueing networks
- production line
- iterative learning control
- incremental learning
- error reduction
- power consumption
- allocation strategy
- real time database systems
- low cost
- flowshop
- production system
- multistage
- database
- single server
- decomposition algorithm
- real time
- dynamic programming
- storage management
- steady state