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A rail-to-rail low-power latch comparator with time domain bulk-tuned offset cancellation for low-voltage applications.
Nima Shahpari
Mehdi Habibi
Published in:
Int. J. Circuit Theory Appl. (2018)
Keyphrases
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low power
high speed
cmos technology
low voltage
mixed signal
power consumption
low cost
single chip
digital signal processing
vlsi architecture
logic circuits
real time
power dissipation
power reduction
low power consumption
vlsi circuits
gate array
design considerations
image sensor
frame rate
power line