A 265- $\mu$ W Fractional- ${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS.
Hanli LiuAtsushi ShiraneKenichi OkadaZheng SunHongye HuangWei DengTeerachot SiriburanonJian PangYun WangRui WuTeruki SomeyaPublished in: IEEE J. Solid State Circuits (2019)