Rtdt: A Front-End for Efficient Model Checking of Synchronous Timing Diagrams.
Nina AmlaE. Allen EmersonRobert P. KurshanKedar S. NamjoshiPublished in: CAV (2001)
Keyphrases
- model checking
- temporal logic
- asynchronous circuits
- formal verification
- finite state
- temporal properties
- formal specification
- reachability analysis
- partial order reduction
- symbolic model checking
- bounded model checking
- automated verification
- formal methods
- epistemic logic
- pspace complete
- finite state machines
- verification method
- model checker
- computation tree logic
- timed automata
- rough sets
- transition systems
- linear temporal logic
- ordered binary decision diagrams
- alternating time temporal logic