Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking.
Aarti GuptaPranav AsharPublished in: VLSI Design (1998)
Keyphrases
- boolean satisfiability
- probabilistic planning
- sat solvers
- boolean optimization
- heuristic search
- branch and bound algorithm
- sat solving
- integer linear programming
- sat problem
- symmetry breaking
- randomly generated
- maximum satisfiability
- binary decision diagrams
- boolean formula
- combinatorial problems
- constraint satisfaction problems
- max sat
- graph coloring
- random sat instances
- satisfiability problem
- constraint satisfaction